Various ceramic ball grid array packages, leadless chip carriers, laminated chip carriers, tape ball grid array packages, and overmolded, globtop, and plastic ball grid array packages are known today. Such packages typically contain a semiconductor device (a chip) and provide for electrical and thermal connection paths to and from the chip, while protecting the chip from extraneous environmental factors, processing chemicals, and handling.
Such packages typically include connections known in the art as solder reflow (or melt) connections. These connections provide for both electrical and thermal conduction paths. It is known from prior art that a reformable solder ball 107 can be attached to contact pad 105 on substrate 103 of electronic package 101, as depicted in FIG. 1. Further, as depicted in FIG. 2, it is known from prior art that solder ball 207 can be attached to contact pad 206 of substrate 204. Typically substrate 204 is circuitized. Solder ball 207 provides a standoff distance s between contact pads 205 and 206; this standoff provides mechanical compliance between the two substrates. It is also known that a higher standoff, with resulting increased compliance, can result in improved resistance to fatigue. The connections may be formed between a chip and a circuitized substrate, serving as a chip carrier package. Examples of circuitized substrates include printed wiring boards, flexible circuit cards, laminated chip carriers, metallized ceramic substrates, and multi-layer ceramic substrates. When a chip is connected to a circuitized substrate with numerous solder reflow connections, this form of connection is also known in the art as “flip-chip” or controlled collapse chip connection (C4), and results in a flip chip package.
Aside from flip chip packages, there are many kinds of chip carrier packages known in the art of semiconductor packaging. Other forms of chip carrier packages include wirebond chip carriers, thermo-compression bond chip carriers, and hybrid chip carrier devices. Further connection of a chip carrier package to a circuit card or board may be accomplished by utilizing known solder reflow methods to obtain what is commonly known as a ball grid array (BGA) connection therebetween. Various circuit cards, usually comprised of several layers of dielectric material, e.g., fiberglass-reinforced epoxy resin, interspersed with various conductor layers, (power, signal and/or ground planes) and often including plated through-holes and/or internal conductive vias, are known in the art.
An inherent problem with either the C4 or BGA connection is that the thermal expansion characteristics of the two objects being connected may differ substantially. For example, the linearized coefficient of thermal expansion (CTE) of silicon is in the 2.5 to 4.0 part per million/degree Celsius (ppm/C) range, while the CTE of a circuitized substrate may be 3 to 25 ppm/C, depending on the material choices. Therefore, the solder connections between a chip and circuitized substrate will be subject to thermally-induced stresses. This stress is generally increased by the use of larger, more complex, higher performance (i.e., more powerful and thermally dissipative) and higher signal count chips. Since many hundreds, and even thousands, of connections may be present in a single chip carrier package, the method of forming the connections must also be reliable, manufacturable, efficient, and economical. In a similar manner, thermal expansion mismatch between a chip carrier package and a circuit card or board may give rise to significant stresses which adversely affect reliability. (A typical printed circuit board composed of common glass-epoxy has a CTE value of 17 to 22 ppm/C, while a chip carrier has a composite CTE value which may vary from 3 ppm/C to 25 ppm/C, depending on geometry and material choices.)
To manage these problems, several strategies are known in the art. Two of these include the use of a stress-relieving underfill (or encapsulant), and the use of high-standoff solder joints including high-melt solder standoffs and solder-coated copper ball standoffs. The use of fatigue resistant solder materials, the use of conductive adhesives to form the C4 or BGA connections, and the use of compliant substrate materials are also known in the art. Each of these methods helps to form reliable connections, but at a cost of manufacturability, restrictive material choice, or other disadvantage. For example, the use of underfill as a stress-relieving method to protect the connections generally prevents subsequent removal and replacement to replace or repair a device (commonly known as rework). The use of a solder-coated copper ball as a standoff-enhancement device results in a higher standoff, but greatly increased joint stiffness. Known solder columns comprise preformed high-temperature solder material. The high-temperature material is required to keep its preformed shape during subsequent solder reflow attachment. The solder column is generally attached to a device with a second, lower-melting solder in conjunction with an alignment fixture. The manufacturability difficulties of the solder column connection method limit the pitch (distance between adjacent columns) of a package interconnection to about 1.0 millimeter (mm) at the present time, and require the use of a hierarchy of solder melt materials.
A method for dynamically forming a solder column instead of preforming the solder column, while retaining a column-like shape during temperature excursions beyond the solder melt temperature would be very desirable. Further, the ability to obtain shapes other than simple columns would be very desirable because the shape of the solder connection can influence the internal stresses, and the reliability of the connection and manufacturability.